1. Field of the Invention
The present invention relates to the circuit design and method of fabrication for an output buffer implemented in an integrated circuit (IC). More particularly, this invention relates to an improved circuit configuration of an output buffer that improves ESD protection without degrading ringing voltage suppression.
2. Description of the Related Art
The output signals from a CMOS I/O buffer often experience a large amount of voltage ringing and overshooting due to the capacitor produced between the wiring elements and the inductance from the IC package and the motherboard on which the CMOS chip is mounted. A common method for suppressing the voltage ringing and overshooting is to solder a series resistor with a resistance of about 10 ohms to the motherboard next to each CMOS I/O pin, as shown in FIG. 1A. The CMOS I/O buffer 10 has an output buffer 12, a sub-ESD protection circuit 14 and an input buffer 16. The output buffer 12 has a pull-high circuit of PMOS P1 and a pull-low circuit of NMOS N1. Since the output buffer 12 has the ability of high current driving, the PMOS P1 and the NMOS N1 both have wide gate-width and can act as a main-ESD protection circuit. The sub-ESD protection circuit 14, as shown in FIG. 1A, has a resistor with a resistance about 200 ohms connected between the pad and input buffer 16 to slow down the ESD effect during an ESD event. Thus, the PMOS P2 and the NMOS N2, which release the ESD stress during an ESD event, can be designed to have a smaller area than that for the output buffer 12. The participation of the external resistor 18 increases the loading of the output buffer and dampens the voltage ringing and overshooting caused by the parasitic capacitors and inductors produced by wiring and packaging. However, an additional part, such as the external resistor 18, is very extravagant in view of motherboard integration. It increases the total area of motherboard and the complexity of part management. Thus, the design in FIG. 1A is not well considered.
Another method for suppressing voltage ringing and overshooting is to remove the external resistor 18 and to add two on-chip resistors connected in series with the PMOS P1 and the NMOS N1 respectively, as shown in FIG. 1B. Thus, the pull-high circuit comprises a PMOS P1 and a resistor Rp, while the pull-low circuit comprises a NMOS N1 and a resistor Rn. The driving ability of the output buffer 18 is less because of the existence of these two resistors, Rp and Rn. Thus the voltage ringing and overshooting at the pad will be smaller. The larger resistance these two resistors, Rp and Rn, have, the better performance of suppressing can be achieved. However, the resistance of the resistors Rp, Rn should not be so large that the driving requirement of the CMOS I/O buffer 20 is not met. For example, the required driving ability of the NMOS N1 is to sink a DC current of about 8 to 10 mA and a maximum transient current of about 40 mA. For a CMOS I/O buffer, the voltage overload (VOL) specification is typically 0.4V. With the sink current in the above range, in order to comply with the limitation of VOL specification, the resistance of the resistor Rn can""t be more than 10 ohm.
The resistor Rn of 10 ohm contributes a voltage of 0.1 volt when the NMOS N1 sinks a DC current of 10 mA and a voltage of 0.4 volt when the NMOS N1 sinks a transient current of 40 mA, thus the pull-low circuit can comply with the VOL specification. Usually, these on-chip resistors Rn, Rp are formed by poly resistors or n-well resistors.
However, while the voltage ringing and overshooting is suppressed, the performance of ESD protection is degraded by the participation of the resistors Rn, Rp. For example, in comparison with the circuit configuration in FIG. 1A, during an ESD event of positive pulse at the pad, the resistor Rn, as shown in FIG. 1B, raises the trigger voltage of the pull-low circuit and induces more ESD stress loading on the sub-ESD protection circuit 14. Thus, the voltage at the sub-ESD protection circuit 14 is higher than before and the probability of ESD damage in the input buffer 16 is increased. Although the resistance of the resistors Rn, Rp is as low as 10 ohm, the discharge current during a ESD event is as large as several amps and makes the trigger voltage at the pad about several ten volts higher than that without the resistor Rn. Thus the resistors Rn, Rp causes the degradation of ESD protection.
Therefore, in the art of circuit design and integrated circuit manufacture, it is needed to provide a circuit configuration with improved ESD protection that suppresses the voltage ringing and overshooting.
It is therefore an object of the present invention to provide a novel and improved buffer for improving ESD protection without causing any adverse effect to the performance of the voltage ringing and overshooting suppression.
Briefly, in a preferred embodiment, the present invention provides a buffer comprising a transistor and a resistance modulator connected in series between an IC pad and a power node. The resistance modulator provides a first resistance during normal circuit operation, i.e., in the absence of an ESD event, and provides a second resistance that is Lower than the first resistance during an ESD event.
The transistor can be an NMOS transistor while the power node is powered by a voltage source VSS during normal circuit operation. Alternatively, the transistor can be a PMOS transistor while the power node is powered by a voltage source VDD during normal circuit operation.
The present invention also provides an output buffer comprising a pull-high circuit and a pull-low circuit. The pull-high circuit connects between a relatively high power node and an IC pad. The pull-low circuit connects between a relatively low power node and the IC pad. The pull-low circuit has an ESD protection device and a resistance modulator connected in series. The resistance modulator provides a first resistance during normal circuit operation, and provides a second resistance that is lower than the first resistance during an ESD event.
The resistance modulator comprises a resistor and a rectifying circuit connected in parallel. The rectifying circuit can be a diode of a first polarity, a plurality of diodes of a first polarity connected in series, or a first diode of a first polarity and a second diode of a second polarity connected in parallel.
It is an advantage of the present invention that the ESD protection ability is improved without decreasing the ability of the voltage ringing and overshooting suppression. During the circuit operation, the rectifying circuit acts as an open circuit, thereby the resistance modulator has a first resistance to suppress the voltage ringing and overshooting. During the ESD event, the voltage across the resistance modulator becomes high enough to impel the rectifying circuit to act as a short circuit. Therefore, the second resistance of the resistance modulator is lower than the first one to avoid too much voltage rising in the pad, causing damage to other internal circuit, during the ESD event.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.